In recent years, a server which can be partitioned into multiple physical partitions in a chassis has received a lot of attention. In such server, all the partitions in the chassis are completely electrically separated with each other. Each partition can be operated as an independent server. Therefore, by using such technology, the servers can be integrated without affecting each other. The server in which physical partitioning can be implemented has a function with which a processor can be dynamically added to the physical partition in a unit so-called a cell which has a processor and a memory.
FIG. 6 is a block diagram showing a configuration of a system which is configured by a cell unit that is a module including a processor and a memory. In the system shown in FIG. 6, each of the cells includes two processors and two memories that correspond to the processors, respectively. Each processor accesses the memory through a bus.
In such system, the processor is dynamically added by a cell unit. In this case, first, an administrator starts up the additional cell as a spare partition. After an initialization process of the processor in the cell has been completed, the administrator installs the cell in the partition physically.
There are two reasons for starting up the cell unit as the spare partition. The first reason is the restriction on the initialization of the additional processor. The second reason is to check whether the processor is reliable in advance.
The restriction on the initialization of the additional processor is that a memory is required for the initialization of the additional processor. The initialization process of the processor typified by Itanium is performed by the PAL (Physics Abstraction Layer) developed by a processor vendor that is an unopened code and the SAL (System Abstraction Layer) developed by the BIOS (Basic Input/Output System) vendor. A procedure of the initialization process of the processor using the PAL and the SAL is specified as the specification. Accordingly, when a user wants to add the spare processor, the user has to follow the specified procedure for performing the initialization process of the processor. The initialization process of the processor includes not only setting of a value required for operating the processor but also failure diagnosing to check the reliability of the processor. The memory is required for the failure diagnosing. When the spare processor is added, a memory for initialization of the processor has to be provided in the additional cell initially because the additional processor can not be accessed from outside during the initialization process.
Thus, there is a restriction on which the memory for the initialization process has to be added together with the additional processor, when the processor is dynamically added to the partition.
For example, a technology for dynamically adding a processor is disclosed in Japanese Patent Application Laid-Open No. 1991-32143. In this technology, when a host processor completes a hardware connection of an additional local processor and all preparations have been completed, the host processor reads out a system file from an external storage device. Next, the host processor loads an initial program to the additional local processor and issues a command to start up a system. Next, the host processor transmits a local processor diagnostic program and issues a command to perform device diagnosis of the additional local processor. Thus, a memory into which the local processor diagnostic program is loaded by the host processor is required in the additional local processor when the additional local processor is added.
Thus, when a processor is dynamically added, a memory for the initialization of the processor has to be added together with the processor. Accordingly, even when a user needs new processor alone, the user has to purchase a memory as well as the processor. Therefore, the user has a difficulty in flexibly modifying a system configuration.
A microcomputer system in which the initialization of a CPU (Central Processing Unit) in a microcomputer board is performed without using a CALL/RET instruction that uses a RAM (Random Access Memory) in order to prevent runaway caused by RAM abnormality is disclosed in Japanese Patent Application Laid-Open No. 1996-054966.
A system configuration control device with which the processing time of configuration control commands is shortened by enabling a memory access from an additional device to a main storage device before the device is logically added to a system is disclosed in Japanese Patent Publication No. 2513769.
FIG. 7 shows a configuration of the Itanium processor. The Itanium processor employs the CSI (Common System Interface). As shown in FIG. 7, the processor employing the CSI includes a CSR (Control Status Register), a memory and a DCROM (Direct Connect Read Only Memory). The CSR is a register of the processor employing the CSI. The memory is used when the processor performs some processes. The DCROM is a nonvolatile memory and stores BIOS firmware for initializing a processor. The processors establish links each other to communicate with each other. Each processor communicates with a NC (Node controller). The processors which employ the CSI can read the DCROM before establishing links each other because the processors employing the CSI each have the DCROM.
A case in which a processor employing the CSI is dynamically added to a system which includes a processor employing the CSI will be described. Here, the case in which a processor which does not have a memory is dynamically added will be described. That is, the case in which the processor including only the CSR and the DCROM is added to the system shown in FIG. 7 will be described. In this case, the processor to be added uses the memory provided in the processor in the system for an initialization process.
As mentioned above, when the processor is dynamically added, the addition of the processor has to be performed after checking the reliability of the additional processor beforehand. Accordingly, an environment in which the additional processor can be started up in an independent memory space from a memory space in which the processor is started up is necessary.
However, as mentioned above, the case in which the additional processor uses a memory provided in the processor in the system in which the additional processor is added to initialize the additional processor, a link between the memory provided in the operating processor and the additional processor is established before checking the reliability of the additional processor. In other words, the case in which the processor with no memory is dynamically added to the system as shown in FIG. 6, the additional processor can not be started up in the independent memory space from the operating processor and the check of the reliability of the additional processor can not be performed before the addition of the additional processor. Therefore, when the additional processor operates improperly, it may affect the processor in the system in which the additional processor is added. Accordingly, there is a problem that the processor with no memory can not be dynamically added to the system including the processor employing the CSI as shown in FIG. 7 as well as to the system that is composed of cell units as shown in FIG. 6.